Parallel input, with channels energized randomly, to parallel output, with channels energized in preferred order means, and same in input of numerical-to-digital code converter



y 1, 1962 c. H. DAVIS ET AL ,03 7

PARALLEL INPUT, WITH CHANNELS ENERGIZED RANDOMLY, TO PARALLEL OUTPUT, WITH CHANNELS ENERGIZED IN PREFERRED ORDER MEANS, AND

SAME IN INPUT OF NUMERICAL-TO-DIGITAL CODE CONVERTER Filed Aug. 11, 1958 2 Sheets-Sheet l Inventors C H DAVlS J. B. STRINGER @fi Z Attorneys II I y 1962 c. H. DAVIS ET AL 3,032,267

PARALLEL INPUT, WITH CHANNELS ENERGIZED RANDOMLY, TO PARALLEL OUTPUT, WITH CHANNELS ENERGIZED IN PREFERRED oRDER MEANS, AND

SAME IN INPUT OF NUMERICALTODIGITAL CODE CONVERTER Filed Aug. 11, 1958 2 Sheets-Sheet 2 AND ' J; SUM.(UNIT$) 2 8 2 CARRY |.(TWOS) 2' A v CARRY 2.(I=ouRsI J l4 l5 5 DELAY INHIBIT FIG. 2

CHARLES HOIJRRD DIM/I5 1! JOHN BENTLEY STRINGER Inventors By Mwm,

Attorneys PARALLEL INPUT, WITH CHANNELS ENERGIZED RANDOMLY, T PARALLEL OUTPUT, WITH CHANNELS ENERGIZED IN PREFERRED OR- DER MEANS, AND SAME 1N INPUT 0F NU- MERICAL-TO-DIGITAL CODE CONVERTER Charles Howard Davis, London, and John Bentley Stringer, Hanworth, England, assignors to National Research Development Corporation, London, England, a British corporation Filed Aug. 11, 1958, Ser. No. 754,231 Claims priority, application Great Britain Aug. 13, 1957 34 Claims. (Cl. 235-172) The present invention relates to electrical computing engines.

An object of the present invention is to provide an adder for a computing engine, and an adder having seven inputs will be described, although the invention is by no means restricted to a seven-input adder.

According to the present invention there is provided an electrical digital adder including two cascades of resistors, each cascade being fed from a separate substantially constant current supply, input means for varying the potential at corresponding points in each cascade to an extent proportional to the number of separate input potentials representing digits to be added and applied to the said means and output means for detecting the polarity of the potential difference between selected pairs of points on the cascades, the points of each pair being on separate cascades so that the number of digits to be added is represented by the number of pairs of points having a potential difference of a predetermined polarity.

The notation used in one of the drawings in the present specification is the well-known Turing notation as de-.

scribed in the specification of US. Patent No. 2,686,632, except that in the present specification delays are shown as D-shaped symbols.

An embodiment of the invention will be described by way of example with reference to the accompanying drawings, in which:

FIGURE 1 is a circuit diagram of the embodiment; and

FIGURE 2 is a diagram of a possible output circuit for an adder of the type shown in FIGURE 1 so as to make it suitable for use in a computing engine constructed to work in the binary scale of notation and in the serial mode.

FIGURE 1 is a circuit diagram of an embodiment of the invention. Seven differentially connected or commonly termed long-tailed pair valves V1, V2, V3, V4, V5, V6 and V7, each of which is a double triode type having a common cathode load and normally conducting on the left-hand side, have all their left-hand anodes joined to a resistor R2, which is joined to earth or ground via a resistor R1 and an inductor L1 in series. The joint or junction of the resistors R1 and R2 is labelled X. The point X is joined to the anode of a constant current triode V10 via eight resistors R3, R11, R12, R13, R14, R15, R16 and R17 in series, the resistor R17 being nearest the anode of the valve V10. The ends remote from the valve V16 of the resistors R11, R12, R13, R14, R15, R16, and R17 are separately connected to the control grids of seven pentode valves V11, V12, V13, V14, V15, V16 and V17 respectively.

The right-hand anodes of the valves V1, V2, V3, V4, V5, V6 and V7 are all joined to a resistor R which is joined to earth or ground via a resistor R4 and an inductor L2 in series. The joint of or junction between the resistors R4- and R5 is labelled Y. The point Y is joined to the anode of a constant-current triode V16 via eight resistors R6, R26, R25, R24, R23, R22, R21 and R20 in series, the resistor R20 being nearest the anode of 3,032,267 Patented May 1, 1962 the valve V10. The ends nearest the valve V10 of the resistors R21, R22, R23, R24, R25, R26 and R6 are separately connected to the control grids of seven pentode valves V11, V12, V13, V14, V15, V16, and V17 respectively.

The left-hand grids of the valves V1, V2, V3, V4, V5, V6 and V7 are separately connected to seven terminals T1, T2, T3, T4, T5, T6 and T7 respectively; and the anodes of the pentode valves V11, V12, V12, V13, V14, V14, V15, V16, V16 and V17 are connected to output terminals 1, 2, 2, 3, 4, 4, 5, 6, 6 and 7 respectively.

The end of the resistor R2 remote from the point X and the end of the resistor R3 remote from the point X are joined by an assisted cathode-follower valve pair V8 and V9, and the end of the resistor R5 remote from the point Y and the end of the resistor R6 remote from the point Y are joined by an assisted cathode-follower valve pair V8 and V9.

The operation of the circuit is as follows. The seven addends are applied to the terminals T1, T2, T3, T4, T5, T6 and T7 of the long-tailed triode pair valves V1, V2, V3, V4, V5, V6 and V7 respectively in the following manner: when a given addend is a one, the corresponding terminal is made to receive a negative voltage; but when given addend is a zero the corresponding terminal re ceives no such negative voltage. The sum, therefore will be the same as the number of terminals that receive negative voltages.

The seven long-tailed pentode pairs V11-V11, V12- V12, V13V13', V14-V14, V15--V15, V16-V16, and V17-V17 given an indication of the sum as follows. When the sum digit is zero, the valves V11, V12, V13, V14, V15, V16 and V17 all conduct. When the sum digit is one, it is arranged in a manner shown below that the valve V11 ceases to conduct and the valve V11 conjducts. When the sum digit is two, it is arranged that the valves V11 and V12 do not conduct but that the valves V11 and V12 do conduct, and so on, so that in general when the sum digit is n, the first n valves of the set V11, V12, V13, V14, V15, V16 and V17 and the last 7-11 valves of the set V11, V12, V13, V15, V16, and V17 conduct.

This is achieved as follows. The potential of the point X is determined by the current through the resistor R1, which is the sum of the currents through the resistors R2 and R3. The current through the resistor R3 is constant, and is determined by the constant-current triode V10. Similarly the potential of the point Y is determined by the current through the resistor R4, which is the sum of the currents through the resistors R5 and R6; and the current through the resistor R6 is constant, and is determined by the constant-current triode V10.

Normally the valves V1, V2, V3, V4, V5, V6 and V7 are all conducting on the left-hand side, so that the current through the resistor R5 is negligible and the current through the resistor R2 is considerable. When a negative voltage is applied to one of the termianls T1, T2, T3, T4, T5, T6 or T7 the corresponding valve V1, V2, V3, V4, V5, V6 or V7, as the case may be, will cease to conduct on the left-hand side and start to conduct on the right, so that an increment of current Will be removed from the resistor R2 and made to flow through the resistor R5. The effect will be to raise the potential of the point X by an increment of voltage and to lower the potential of the point Y by an increment of voltage. Since the right-hand grid potential of each of the valves V1, V2, V3, V4, V5, V6 and V7 is rather lower than its (normal) left-hand grid potential, the right-hand cathode potential will be rather lower than its left-hand cathode potential, and hence the voltage across the lefthand cathode resistor will be greater and so will the current through this resistor. However, the increments of IJ' voltage by which the voltage of the points X and Y change are made the same because the resistance of the resistor R4 is slightly greater than that of the resistor R1. Similarly, when a negative voltage is applied to more valves V1, V2, V3, V V5, V6, and V7 and to the re sistor chain R26, R21, R22, R23, R24, R25, R26 and R6. The current passed by each valve in the set V1, V2, V3, V4, V5, V6 and V7 is about 12 milliamperes when it is than one of the terminals T1, T2, T3, T4, T5, T6, and 5 conducting on the left-hand side, and about 11 milliam T7, the potential of the point X will rise and the potential peres when it is conducting on the right-hand side, and of the point -Y will fall by a number of such equal increthe constant current emitted by each valve V and V10 ments, the number being the same as the number of teris about 6 milliamperes. Thus when all seven valves V1, minals to receive negative voltages. V2, V3, V4, V5, V6 and V7 are conducting on the left- Since the current through the resistor R3, and hence 10 hand side the current through the resistor R2 is about through the resistor chain R11, R12, R13, R14, R15, R16 84 milliamperes. and R17, is constant and is determined by the triode valve The potential of the point X is determined by the cur- Vlt), these changes in the potential of the point X will rent flowing through the resistor R1, viz. 90 milliamperes produce exactly similar changes in the potentials of the when all the valves V1, V2, V3, V4, V5, V6, and V7 resistors R3, R11, R12, R13, R14, R15, R16 and R17, are conducting on the left-hand side, and its resistance, and will thus produce exactly similar changes in the poviz. 560 ohms. The potential is thus -50.4 volts, and vtentials of the control grids of the pentodes V11, V12, is written -50 volts in the table for simplicity. Since V13, V14, V15, V16 and V17. the current passed by the valve V111 is a constant one In the same way since the current through the resistor of 6 milliamperes, the potential of the control grid of R6, and hence through the resistor chain R26, R25, R24, the valve V11 will aways be 6 volts below that of the R23, R22, R21 and R20, is constant and determined by point X by virtue of the resistor R3. Similarly the pothe triode valve V10 these changes in the potential of tential of the control grid of the valve V12 will always the point Y will produce exactly similar changes in the be 6 volts below that of the control grid of the valve potentials of the resistors R20, R21, R22, R23, R24, R25, V11, and so on, so that when the potential of the point R26 and R6, and will thus produce exactly similar changes X is 50 volts, the potentials of the control grids of in the potentialsof the control grids of the pentodes the valves V11, V12, V13, V14, V15, V16 and V17 are V11, V12, V13, V14, V15, V16 and V17. -56, 62, -68, -74, -80, -86 and 92 volts respec- The action of the circuit is more easily understood tively. by reference to the following table, which shows voltages The potential of the point Y when the valves V 1, V2, and currents occurring in various parts of the circuit at V3, V4, V5, V6 and V7 are all conducting on the leftvarious times: hand side, determined by the current flowing through the LR hi z 11 11 11 12 12' 13 13' v14 14' 15 15' 16 16 17 17 y Inthe first column L indicates the number of valves resistor R4 (6 milliamperes) and its resistance (587 in the set V1, V2, V3, V4, V6 and V7 which are conductohms), is -4 volts, and in a parallel way to the above, ing on the left-hand side, and R indicates the number of the control grid potentials of the valves V17, V16, V15, valves in that set which are conducting on the right-hand V14, V13, V12, and V11 will be -10, -16, -22, side. At any given time, of course, these two numbers -28, 34, -40 and 46 volts respectively. add up to seven and the latter number (indicated by R) When one of the valves V1, V2, V3, V4, V5, V6 or will give the sum required. In the second column i and V7 starts to conduct on the right-hand side, 12 millii give the currents through the resistors R2 and R5 reamperes of current are removed from the resistor R2 spectively in milliamperes. In the third to eighth 001- and 11 milliamperes of current are made to flow in the umns, x, y, 11, 11', 12, 12', 13, 13, 14, 14', 15, 15', resistor R5. Thus the potential drop across the resistor 16, 16', 17 and 17' give the voltages (in volts) of the R1 will decrease by 6.7 volts and that across the resistor points X and Y, and the control grids .of the pentodes R4 will increase by the same voltage. Because the valves V11, V11, V12, V12, V13, V13, V14, V14, V15, V15, V11) and V10 supply constant currents, the potentials of V16, V16, V17 and V17 respectively. For convenience 65 the control grids of the valves V11, V12, V13, V14, V15, the voltage y of the point Y is given again in the ninth V116 and V17 will rise by the same voltage by which the and last column. For simplicity all values have been potential of the point X has risen, viz. 6.7 volts, and the given to the nearest whole number only. In each line potentials of the control grids of the valves V11, V12, of the table those values pertaining to the left-hand side V13, V14, V15, V16 and V17 will fall by the same 'of the valves V1, V2, V3, V4, V5, V6 and V7 and to voltage. Thus the control grid of the valve V11 is raised the resistor chain R3, R11, R12, R13, R14, R15, R16 to a higher potential than that of the control grid of the and R17, i.e. the columns labelled L, i x, ll, 12, 13, 14, valve V11, so that the current through the cathode load l5, l6 and 17, have been placed slightly above the colresistor R31 will flow through the valve V11 instead of unms labelled R, i y, 11, 12', l3, 14, 15, 16', and 17', the valve V11, which is the desired result. 1

'the values in which pertain to the righthand side of the When a second valve in the set consisting of the valves V1, V2, V3, V4, V5, V6 and V7 conducts on the righthand side, the potentials of the point X and Y rise and fall respectively by a further 6.7 volts as before, which has the effect of lowering the potentials of points of the resistor chain R20, R21, R22, R23, R24, R25, R26 and R6 and raising the potentials of the points of the resistor chain R3, R11, R12, R13, R14, R16, and R17, in each case by 6.7 volts, cutting off the valve V12 and allowing the valve V12 to conduct.

In the same way, the number of valves which conduct in the set consisting of the valves V11, V12, V13, V14, V15, V16 and V17 is the same as the number of valves which conduct on the right-hand side, in the set consisting of the valves V1, V2, V3, V4, V5, V6, and V7, and the valves in the set consisting of the valves V11, V12, V13, V14, V15, V16 and V17 always conduct, so to speak, in turn; that is to say, a valve in the set will only conduct when its left-hand neighbour (if it has one) is conducting. In the table a bold line is used to indicate the division between valves in the set consisting of the valves V11, V12, V13, V14, V15, V16 and V17 conducting and not conducting.

The assisted cathode-followers consisting of the valves V8 and V9 and of the valves V8 and V9 are employed to speed up the operation of the circuit. The action of the valve V9 on the conventional cathode-follower valve V8 is as follows. Should the cathode potential of the valve V8 be slow to follow its grid potential up or down then the action of the anode of the valve V8 on the grid of the valve V9, which will sufit'er a fall or rise in potential, as the case may be, is to decrease or increase the current flowing through the valve V9, giving a large rise or fall in the anode potential and ensuring a prompt response. The action of the assisted cathode-follower consisting of the valves V8 and V9 is precisely the same.

The action of the inductor L1 is to oppose a change of current in itself. A change of current will occur when one of the valves in the set consisting of the valves V1, V2, V3, V4, V5, V6 and V7 stops conducting on one side and starts conducting on the other. In the case where the current through the resistor R1 is decreased, raising the potential of the point X, the back E.M.F. in the inductor is such as to assist in this rise of potential, and, conversely, where the current is increased, lowering the potential, the back is such as to assist in the lowering of the potential. The inductor L2 acts in a similar way.

To increase the speed of the device capacitors having a capacity of 0.02 ,u.f. are inserted in parallel with each of the resistors R11, R12, R13, R14, R15, R16, R21, R22, R23, R24, R25 and R26. These capacitors improve the high-frequency response of the couplings, which is otherwise limited by stray capacity, especially the stray capacity between the anodes of the valves V1, V2, V3, V4, V5, V6 and V7 and earth or ground.

The valves V11, V11, V12, V12, V13, V13, V14, V14, V15, V15, V16, V16, V17 and V17 are pentodes because of the enherently shorter grid base, which enables smaller voltage steps to be used, so that the resistors R1 and R4 can be made smaller than would otherwise be the case, again improving the response of the adder to fast signals. The practical lower limit on the voltage swings is defined by the need to maintain reliable operation in the face of variations in supply voltages and resistor values. This also limits the number of inputs such a device can have.

With these arrangements the speed of response is such that the adder can be used in, for example, a computing engine with a /a microsecond pulse time.

FIGURE 2 is a diagram of a possible output for the adder circuit proper shown in FIGURE 1 and for use in a computing engine constructed to work in the binary system and in the serial mode.

In FIGURE 2, the adder proper, that is to say the part of the embodiment which represents the circuit of FIGURE 1, is labelled A. The channels in FIGURE 2 representing the outputs from the FIGURE 1 terminals 1, 2, 2, 3, 4, 4, 5, 6, 6' and 7 are labelled the same as those terminals respectively. Bars are placed across the channels 2, 4 and 6 since the signals on them are complementary to those on the channels 2, 4 and 6 respectively. The channels 1 and 2 feed into an AND- gate 8, the channels 3 and 4 feed into an AND-gate 9, and the channels 5 and 6 feed into an AND-gate 10. The outputs of the AND-gates 8, 9 and 10, together with the channel 7, feed into a channel labelled SUM. The channels 2 and 4 feed into an AND-gate 11, whose output, together with the channel 6, is fed into a onedigit delay 12, and thence to a channel labelled CARRY 1 via an inhibiting gate 13. The channel 4 feeds into a two-digit delay 14 and thence to a channel labelled CARRY 2 via an inhibiting gate 15.

A signal on a channel labelled C.S. is arranged (when it is on) to inhibit the gate 13, and also to inhibit the gate 15 via a buffer 16. The channel C.S. is also applied to the buffer 16 via a one-digit delay 17.

The circuit will produce three outputs, viz. a units output, a twos output and a fours output, and for each sum these are determined by the binary form of the number (call-ed the sum) of valves in the set consisting of the valves V11, V12, V13, V14, V15, V16, and V17 conducting. These are set out in the following table:

Sum Outputs decimal binary units twos fours notation notation In the table the binary notation is used with the least significant digit leading.

The units output is a one whenever there is an output on the channel 1 and no output on the channel 2 (that is, outputs on both the channels 1 and 2), or outputs on both the channels '3 and 4, or outputs on both the channels 5 and 6' or an output on the channel 7. This is provided by the gates 8, 9 and 10, and the channel 7, all of which feed into the channel labelled SUM. This channel, therefore, gives the units digit.

The twos output is a one when there is an output in the channel 2 but not on the channel 4, and when there is an output on the channel 6. (When the sum is three there is still an output on the channel 2 and not on the channel 4.) This output is provided in the same Way as the above by the gate 11 and the channel 6, both of which feed into the channel labelled CARRY 1 via the one-digit delay 12 which is necessary to re-tirne the carry so that the output of the channel CARRY 1 can be fed directly into the input of the adder.

The tours output is a one whenever the sum is four or more, and therefore is the same as the signal on the channel 4. This signal must, of course be delayed by two digits (which is achieved by the delay 14) and then be fed back to the input of the adder (which is done via the channel CARRY 2).

These two carry channels may be applied to two of the seven inputs of the adder A, leaving five for the proper addends.

It is well-known that at the end of an addition process the carry digits must be suppressed. This question is discussed in, for example, United Kingdom Patent Number 717,114, as well as in the corresponding United States Patent Number 2,686,632, and this is achieved in the present embodiment by a signal on the channel marked 7 C8. When this signal, which lasts for exactly one digit period, is operative it inhibits the twos carry at the gate 13 for one digit and the fours carry at the gate 15 for two digits (due to the action of the bulfer 16 and the delay 17).

It will be obvious to those skilled in the art that this circuit has far-reaching applications in the computer field apart from the use as an adder described above. For example, by rearranging the gates in the embodiment described by way of reference to FIGURE 2, an encoder may be made; and by weighting the valves V1, V2, V3, V4, V5, V6, and V7 the apparatus will act as a decoder. Any of the valves V1, V2, V3, V4, V5, V6 or V7 may be weighted, for example by halving its cathode resistance so that it would conduct twice as much current as otherwise, and a signal on its grid would be Worth two ordinary signals.

We claim:

1. An electrical digital adder including two cascades of resistors, each cascade being fed from a separate substantially constant current supply, input means for varying the potential at corresponding points in each cascade to an extent proportional to the number of separate input potentials representing digits to be added and applied to the said means and output means for detecting the polarity of the potential difference between selected pairs of points on the cascades, the points of each pair being on separate cascades so that the number of digits to be added is represented by the number of pairs of points having a potential difierence of a predetermined polarity.

2. An electrical digital adder as in claim 1 and in which the input means includes differentially connected pairs of thermionic valves the separate anodes of each such pair being connected to points at the ends of the separate cascades.

3. An electrical digital adder as in claim 1 and in which the output means includes differentially connected pairs of thermionic valves each control grid of each such pair being connected to a separate one of each of the said selected pair of points on the cascades.

4. An electrical digital adder as in claim 1 and in which the output means includes differentially connected pairs of thermionic pentode valves each control grid of each such pair being connected to a separate one of each of the said selected pair of points on the cascades.

5. An electrical digital adder as in claim 1 and in which a capacitor is connected in parallel with each resistor of each cascade.

6. An electrical digital adder as in claim 1 and in which the output of the input means is applied to a cathode follower and the output of the cathode follower is used to regulate the potential of a cascade.

7. An electrical digital adder as claimed in claim 6 and in which the cathode follower is an assisted cathode follower.

8. An electrical signal translating device including a first cascade of resistors and a second cascade of resistors, each cascade being fed from a separate substantially constant current supply, a plurality of input means each connected to raise, when stimulated, the potential of the Whole of the first cascade by an increment of voltage and to lower, when stimulated, the potential of the whole of the second cascade by the same increment of voltage, a plurality of potential comparing means the first of which is connected to the end remote from the current supply of the fi-rstcascade of resistors and to the end adjacent to the current supply of the second cascade of resistors, the second being connected to the first cascade of resistors at a point removed from the first comparing means towards the current supply by one resistor and to the second cascade of resistors at a point removed away from the current supply by one resistor, and so on, whereby the states of the potential comparing means give an indication of the stimulation of the input means. i 9. An electrical signal translating device as in claim 8 and in'which each of the said potential comparing means includes a pair of thermionic valves having a common cathode load.

10. An-electrical signal translating device as in claim 8 and in which each of the said potential comparing means includes a pair of thermionic pentode valves.

11. An electrical signal translating device as in claim 8 and in which each said input means includes a pair of thermionic valves having a common cathode load, the anode of each thermionic valve being connected separately to the end remote from the current supply of each cascade.

12. An electrical signal translating device as in claim 11 and in which each of the said potential comparing means includes a pair of thermionic valves having a common cathode load.

13. An electrical signal translating device as in claim 11 and in which each of the said potential comparing means includes a pair of thermionic pentode valves.

14. A device as in claim 8 and further including a plurality of condensers respectively paralleling the resistors of each cascade.

15. A device as in claim 8 and further including cathode follower means for applying the output of the input means to the cascades to regulate the potential thereof.

16. A device as in claim 15 wherein the cathode follower means includes an assisted cathode follower.

17. A signal translating device comprising a first impedance chain including a plurality of serially connected impedances, a second impedance chain including another plurality of serially connected impedances, means for establishing a reference voltage for each of said chains and for simultaneously changing the reference voltage of each chain by at least one given amount but in opposite directions while maintaining the voltage drop across each of the said impedances substantiallyconstant regardless of any change in the associated reference voltage, the arrangement being such that any point between and including the remote ends of the said serially connected impedances in each chain varies in absolute potential in correspondence with any variance in the associated reference voltage and means for comparing the absolute potentials of at least two given points respectively in said chains.

18. A device as in claim 17 wherein the last mentioned means initially establishes the reference voltage for the first chain at a first value and for the second chain at a second and different value and is capable of varying the first chain reference voltage from said first value toward and to said second value in any one of a given number of different size steps and simultaneously of varying the second chain reference voltage fromthe said second value toward and to the said first value in like manner.

19. A device as in claim 18 and further including a plurality of output meanseach of which is coupled to a different point in each of said chains for effectively indicating the size of the step voltage by which each initial reference voltage is changed. 7

20. A device as in claim 17 wherein said impedances respectively include resistors of substantially equal value.

21. A device as in claim 17 and further including a plurality of condensers respectively in parallel with said resistorsfor increasing the operating speed of the said device.

22. A device as in claim 17 wherein the last mentioned means includes means for feeding to one end of each chain a separate substantially constant current to cause the voltage drop across each of said impedances in each chain to stay substantially constant as aforesaid.

23. A device as in claim 17 and further including means associated with the reference voltage changing means for increasing .the operating speed of the sai device.

24. A device as in claim 23 wherein the further included means comprises a cathode follower.

25. A device as in claim 23 wherein the further included means includes an assisted cathode follower for each of said chains.

26. A signal translating device comprising a first impedance chain including a plurality of serially connectedl impedances, a second impedance chain including a like plurality of other serially connected impedances, means for establishing and then initially changing the absolute voltage at various points along one of said chains by at least one given amount in at least one given direction and at corresponding points along the other chain by a corresponding amount but in an opposite direction, means for maintaining the voltage drop across the said impedances in each chain substantially constant regardless of any change in said absolute voltages, and means for comparing the absolute voltages at given ones of said points respectively in said chains.

27. A signal translating device comprising a first impedance chain including n serially connected impedances, a second impedance chain including other 11 serially connected impedances, means for feeding each of said impedance chains with a separate substantially constant current, input means for causing a reference voltage for the first chain to change to any one of a plurality of different values to effect a corresponding voltage change at n separated points along the first chain, a reference voltage for the second chain to change an amount substantially equal to the instant said reference voltage change of the first chain but in direction opposite thereto to effect a corresponding voltage change at n separated points along the second chain, and n voltage sensitive output means each coupled to a different one of the said It points in each of said chains for respectively measuring the differential potential between each of the n points of the first chain and a respective different given one of the n points of the second chain where said given one is in number the complement on (n+1) of m which is the number of the corresponding first chain point, the n points in both chains being numbered similarly from like ends of the chains.

28. A device as in claim 27 wherein each of the n impedances in each of said chains have a given resistance value, the current feeding means are respectively coupled to said chains at one end thereof, the input means causes the variable reference voltages at the other ends of said chains, and (n-l) of said n points in each chain are respectively the junctions between successive impedances and numbered from the respective said other ends with nth point of each chain being the junction between the nth impedance and the respective current feeding means, whereby the output means indicates to which one of the said plurality of different values the first chain reference voltage is changed by the input means.

29. A device as in claim 28 wherein the input means is capable of changing the said reference voltages respectively from initial first and second values towards each other by any one of n different size steps and the said output means effectively indicates which of these steps is instantly applied by the input means.

30. A device as in claim 29 wherein the input means is characterized by causing said n different size steps to have successively a substantially constant potential differential.

31. A device as in claim 8 and further including means for producing a multi-digit output indicative of the number of potential comparing means in a given state.

32. A device as in claim 31 and in which the multidigit output is in binary notation.

33. A device as in claim 28 and further including means, connected to the said output means, for producing multi-digit output indicative of the value indicated by the output means.

34. A device as in claim 33 and in which the multidigit output is in binary notation.

References Cited in the file of this patent UNITED STATES PATENTS 2,404,250 Rajchman July 16, 1946 2,545,924 Johnstone Mar. 20, 1951 2,658,139 Abate Nov. 3, 1953 2,697,549 Hobbs Dec. 21, 1954 2,765,405 Gamarekian Oct. 2, 1956 2,803,983 Uttley et al. Dct. 8, 1957 2,862,660 Purrell Dec. 2, 1958 2,869,785 Adams Jan. 20, 1959 

